P2IP: A novel low-latency Programmable Pipeline Image Processor

International audienceThis paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P 2 IP. The P 2 IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurabil-ity of the P 2 IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P 2 IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P 2 IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications

Reconfiguration dynamique partielle des systèmes embarqués pour les applications de sécurité routière et les applications multimédias

Short time-to-market windows, high design and fabricationcosts, and fast changing standards of application-specificprocessors, make them a costly and risky investment for embedded system designers.To overcome these problems, embedded system designersare increasingly relying on Field Programmable Gate Arrays(FPGAs) as target design platforms. FPGAs are generally slower and consumemore power than application-specific integrated circuits(ASICs), and this can restrict their use to limited applicationdomains. However, recent advances in FPGA architectures,such as dynamic partial reconfiguration (DPR), are helpingbridge this gap. DPR reduces area and enables mutually exclusive subsystemsto share the same physical space on a chip. It also reducescomplexity, which usually results in faster circuits and lowerpower consumption. The work in this PhD targets first a Driver Assistant System (DAS) system based on a Multiple Target Tracking (MTT) algorithm as our automotive base system. We present a dynamically reconfigurable filtering hardwareblock for MTT applications in DAS. Our system shows thatthere will be no reconfiguration overhead because the systemwill still be functioning with the original configuration until thesystem reconfigures itself. The free reconfigurable regions canbe implemented as improvement blocks for other DAS systemfunctionalities. Two approaches were used to design the filtering block according to driving conditions. We then target another application on the basis of DPR, the H.264 encoder as a multimedia system. Regarding the H.264 multimedia system, we propose a reconfigurable H.264 Motion Estimation (ME) unit whose architecture can be modified to meet specific energy and image quality constraints. By using DPR, we were able to support multiple configurations each with different levels of accuracy and energy consumption. Image accuracy levels were controlled via application demands, user demands or support demands.Les processeurs programmables sont largement utilisés dans la réalisation des systèmes embarqués en raison leurs caractéristiques micro-architecturales intéressantes. Cependant, les délais de plus en plus courts de mise sur le marché et les coûts de conception élevés exigent un investissement coûteux. Pour surmonter ces problèmes, les concepteurs de systèmes embarqués s’appuient de plus en plus sur les circuits reconfigurables (ou FPGA pour Field Programmable Gate Arrays) en tant que plateformes spécifiques de conception. Néanmoins, ces FPGAs sont généralement relativement lents et consomment une quantité importante d’énergie électrique. Cependant, les récentes avancées dans les architectures FPGA, telle que la reconfiguration partiellement dynamique (ou DPR pour Dynamic Partial Reconfiguration), aident à combler ce fossé. La DPR permet à une partie du système embarqué d’être reconfigurée en cours de l’exécution de l’application. Ce qui permet d’avoir une meilleure adéquation entre les besoins des applications exécutées et l’architecture du système. Le travail de cette thèse vise à exploiter les caractéristiques de la DPR des récents FPGAs pour supporter des applications de sécurité routière (ou DAS pour Driver Assistant System) et des applications multimédias où nous avons sélectionné l’encodeur H.264 comme exemple illustratif. Pour l’application DAS, un filtre hardware et reconfigurable dynamiquement a été conçu. Cette architecture ne provoque aucune surcharge de reconfiguration. En se basant sur l’analyse des caractéristiques (nombre, distance, vitesse, etc.) autour du véhicule la meilleure architecture du filtre est déterminée. Concernant l’application H.264, nous avons proposé une nouvelle architecture de l’unité de mesure d’estimation du mouvement (ou ME pour Motion Estimation). L’architecture proposée peut répondre rapidement et automatiquement à des contraintes spécifiques d’énergie et de qualité d’image

Experimental and Theoretical Investigation of Pitting Corrosion of Nickel in Chloride Solution

244 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.Pitting corrosion of nickel in 0.5M NaCl (pH 6.3) was investigated with use of single corrosion pits under both stagnant and flow conditions. The pit dissolution current was found to vary as a function of the applied potential. The pit surfaces were crystallographic, although the general shape of the pits observed was approximately hemispherical. A mathematical model was developed to simulate pitting under stagnant conditions in an axisymmetric domain which closely resembled the actual pit geometry. The model included metal ion complexation, surface kinetics, and transport by migration and diffusion. Potential dependent dissolution was simulated with use of the Tafel expression and found to represent adequately the experimental data over the range of potentials studied.Measurement of pit current as a function of time was made for various hydrodynamic conditions. It was found that, for pits which initiated under stagnant conditions, the sudden imposition of flow caused pit repassivation provided that the pit Peclet number (Pe) exceeded about 1000. At lower Pe, the flow was not sufficient to deactivate the pits, although a decrease in the pit dissolution current was observed. The mathematical model was extended to simulate pit growth in the presence of flow. Theoretical calculations predicted a drop in the pit dissolution current due to flow, in agreement with experimental observations. In addition, theoretical calculations of Pe = 1000 showed rinsing of the pit cavity. Thus, pit repassivation at high Pe occurred owing to disruption of the local pit environment by the flow.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD

Dynamically and Partially Reconfigurable Embedded System Architecture for Automotive and Multimedia Applications

Les processeurs programmables sont largement utilisés dans la réalisation des systèmes embarqués en raison leurs caractéristiques micro-architecturales intéressantes. Cependant, les délais de plus en plus courts de mise sur le marché et les coûts de conception élevés exigent un investissement coûteux. Pour surmonter ces problèmes, les concepteurs de systèmes embarqués s appuient de plus en plus sur les circuits reconfigurables (ou FPGA pour Field Programmable Gate Arrays) en tant que plateformes spécifiques de conception. Néanmoins, ces FPGAs sont généralement relativement lents et consomment une quantité importante d énergie électrique. Cependant, les récentes avancées dans les architectures FPGA, telle que la reconfiguration partiellement dynamique (ou DPR pour Dynamic Partial Reconfiguration), aident à combler ce fossé. La DPR permet à une partie du système embarqué d être reconfigurée en cours de l exécution de l application. Ce qui permet d avoir une meilleure adéquation entre les besoins des applications exécutées et l architecture du système. Le travail de cette thèse vise à exploiter les caractéristiques de la DPR des récents FPGAs pour supporter des applications de sécurité routière (ou DAS pour Driver Assistant System) et des applications multimédias où nous avons sélectionné l encodeur H.264 comme exemple illustratif. Pour l application DAS, un filtre hardware et reconfigurable dynamiquement a été conçu. Cette architecture ne provoque aucune surcharge de reconfiguration. En se basant sur l analyse des caractéristiques (nombre, distance, vitesse, etc.) autour du véhicule la meilleure architecture du filtre est déterminée. Concernant l application H.264, nous avons proposé une nouvelle architecture de l unité de mesure d estimation du mouvement (ou ME pour Motion Estimation). L architecture proposée peut répondre rapidement et automatiquement à des contraintes spécifiques d énergie et de qualité d image.Short time-to-market windows, high design and fabricationcosts, and fast changing standards of application-specificprocessors, make them a costly and risky investment for embedded system designers.To overcome these problems, embedded system designersare increasingly relying on Field Programmable Gate Arrays(FPGAs) as target design platforms. FPGAs are generally slower and consumemore power than application-specific integrated circuits(ASICs), and this can restrict their use to limited applicationdomains. However, recent advances in FPGA architectures,such as dynamic partial reconfiguration (DPR), are helpingbridge this gap. DPR reduces area and enables mutually exclusive subsystemsto share the same physical space on a chip. It also reducescomplexity, which usually results in faster circuits and lowerpower consumption. The work in this PhD targets first a Driver Assistant System (DAS) system based on a Multiple Target Tracking (MTT) algorithm as our automotive base system. We present a dynamically reconfigurable filtering hardwareblock for MTT applications in DAS. Our system shows thatthere will be no reconfiguration overhead because the systemwill still be functioning with the original configuration until thesystem reconfigures itself. The free reconfigurable regions canbe implemented as improvement blocks for other DAS systemfunctionalities. Two approaches were used to design the filtering block according to driving conditions. We then target another application on the basis of DPR, the H.264 encoder as a multimedia system. Regarding the H.264 multimedia system, we propose a reconfigurable H.264 Motion Estimation (ME) unit whose architecture can be modified to meet specific energy and image quality constraints. By using DPR, we were able to support multiple configurations each with different levels of accuracy and energy consumption. Image accuracy levels were controlled via application demands, user demands or support demands.VALENCIENNES-BU Sciences Lettres (596062101) / SudocSudocFranceF

Scalable shared-memory architecture to solve the Knapsack 0/1 problem

International audienceDynamic Programming (DP) is used to solve combinatorial optimization problems and constitutes one of the 13 High Performance Computing (HPC) patterns. DP suffers from irregular, data-dependent memory accesses that deteriorates performance. The Knapsack 0/1 belongs to the simplest DP algorithms which is called Serial Monadic and has been treated in software with cache-efficient algorithms as well as parallel threads, OpenMP or MPI